Evaluation of Space-Time Block Codes Under Controlled Fading Conditions Using Hardware Simulation

Abstract

Space time block codes (STBC) are a type of multiple input multiple output (MIMO) communications system that encode blocks of information into symbol sequences sent simultaneously from multiple antennas. MIMO communications systems have shown channel capacity improvement in multipath digital communications environments. The STBC class of MIMO communications systems can be easily decoded using linear combination and is resilient in the face of multipath channel effects. MIMO systems have traditionally been studied using theoretical analyses, simulations and real signal based experiments. Probabilistic models simulate channel effects as random variables, but are only estimates of actual conditions. Real signal experiments evaluate system performance under real-world conditions, but are not readily repeatable. Both modeling methods evaluate system performance in terms of the aggregate results. This dissertation research presents an approach that introduces controlled attenuation and delay to probabilistic channel models. This method allows the evaluation of MIMO system performance under specific channel conditions. The approach is demonstrated with a hardware accelerated STBC system model that is used to evaluate the performance of a MIMO system under controlled path conditions. The STBC system model utilizes a Xilinix® programmable gate array (PGA) device as a hardware accelerator. The model exploits the parallel processing capability of the PGA to simulate a nine path channel model and a three antenna rate ½ STBC. Novel implementations are developed for the additive white Gaussian noise (AWGN) sources and the linear MIMO decoding in PGA hardware. The model allows specification of overall noise and multipath fading effects for the channel as well as attenuation and phase delay for each channel path. Performance of the communications system is evaluated in terms of bit error rate (BER) versus signal-to-noise ratio (SNR). Hardware acceleration greatly reduces the time required to obtain simulation results. Reduced simulation time improves the use of the model by allowing evaluation of system performance under a greater number of conditions, greater performance curve resolution and evaluation at lower BER. The processing rate of the hardware accelerated model is compared to an equivalent software model. The model also provides an extensible platform for future research in communications theory.