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dc.contributor.advisorObeid, Iyad
dc.creatorBalasubramanian, Karthikeyan
dc.date.accessioned2020-10-20T13:33:26Z
dc.date.available2020-10-20T13:33:26Z
dc.date.issued2011
dc.identifier.other864885215
dc.identifier.urihttp://hdl.handle.net/20.500.12613/727
dc.description.abstractAnalyzing the brain's behavior in terms of its neuronal activity is the fundamental purpose of Brain-Machine Interfaces (BMIs). Neuronal activity is often assumed to be encoded in the rate of neuronal action potential spikes. Successful performance of a BMI system is tied to the efficiency of its individual processing elements such as spike detection, sorting and decoding. To achieve reliable operation, BMIs are equipped with hundreds of electrodes at the neural interface. While a single electrode/tetrode communicates with up to four neurons at a given instant of time, a typical interface communicates with an ensemble of hundreds or even thousands of neurons. However, translation of these signals (data) into usable information for real-time BMIs is bottlenecked due to the lack of efficient real-time algorithms and real-time hardware that can handle massively parallel channels of neural data. The research presented here addresses this issue by developing real-time neural processing algorithms that can be implemented in reconfigurable hardware and thus, can be scaled to handle thousands of channels in parallel. The developed reconfigurable system serves as an evaluation platform for investigating the fundamental design tradeoffs in allocating finite hardware resources for a reliable BMI. In this work, the generic architectural layout needed to process neural signals in a massive scale is discussed. A System-on-Chip design with embedded system architecture is presented for FPGA hardware realization that features (a) scalability (b) reconfigurability, and (c) real-time operability. A prototype design incorporating a dual processor system and essential neural signal processing routines such as real-time spike detection and sorting is presented. Two kinds of spike detectors, a simple threshold-based and non-linear energy operator-based, were implemented. To achieve real-time spike sorting, a fuzzy logic-based spike sorter was developed and synthesized in the hardware. Furthermore, a real-time kernel to monitor the high-level interactions of the system was implemented. The entire system was realized in a platform FPGA (Xilinx Virtex-5 LX110T). The system was tested using extracellular neural recordings from three different animals, a owl monkey, a macaque and a rat. Operational performance of the system is demonstrated for a 300 channel neural interface. Scaling the system to 900 channels is trivial.
dc.format.extent163 pages
dc.language.isoeng
dc.publisherTemple University. Libraries
dc.relation.ispartofTheses and Dissertations
dc.rightsIN COPYRIGHT- This Rights Statement can be used for an Item that is in copyright. Using this statement implies that the organization making this Item available has determined that the Item is in copyright and either is the rights-holder, has obtained permission from the rights-holder(s) to make their Work(s) available, or makes the Item available under an exception or limitation to copyright (including Fair Use) that entitles it to make the Item available.
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/
dc.subjectElectrical Engineering
dc.subjectEngineering, Biomedical
dc.subjectNeurosciences
dc.subjectFuzzy Logic Hardware
dc.subjectFuzzy Spike Sorter
dc.subjectNeural Signal Processing
dc.subjectReconfigurable System-on-chip
dc.subjectScalable and Real-time Hardware
dc.subjectSpike Detection and Sorting
dc.titleReconfigurable System-on-Chip Architecture for Neural Signal Processing
dc.typeText
dc.type.genreThesis/Dissertation
dc.contributor.committeememberKiani, Mohammad F.
dc.contributor.committeememberYantorno, Robert E.
dc.contributor.committeememberHelferty, John J.
dc.contributor.committeememberShi, Justin Y.
dc.description.departmentElectrical and Computer Engineering
dc.relation.doihttp://dx.doi.org/10.34944/dspace/709
dc.ada.noteFor Americans with Disabilities Act (ADA) accommodation, including help with reading this content, please contact scholarshare@temple.edu
dc.description.degreePh.D.
refterms.dateFOA2020-10-20T13:33:26Z


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