DESIGN FOR BIT ERROR RATE ESTIMATION OF HIGH SPEED SERIAL LINKS

Abstract

High-speed serial links in modern communication systems often require the Bit-Error-Rate (BER) to be at the level of 10 −12 or lower. From the industry perspective, major drawbacks in high volume production test for the serial links with low BER are the excessive test time for comparing each captured bit for error detection and costly instrumentation. In this thesis, we focus on developing a novel BER estimation methodology and its implementation. We propose a novel BER estimation methodology and an effective self-test system, which not only eliminates the usage of expensive measuring instruments, but also significantly reduces the test time. In the proposed BER estimation, we show that the total jitter (TJ) spectral information of a test SerDes is successfully estimated from the known TJ distribution of a golden SerDes. We propose a novel BER estimation formula that incorporates not only the TJ spectral information of the serial data, but also the TJ spectral information of the recovered clock. Our proposed estimation formula enables efficient BER estimation without excessive test time, and its accuracy does not depend on the jitter present in the serial data stream of the SerDes. The experimental results demonstrate that the test time for the proposed BER estimation is in the order of seconds, which translates to the test time savings of more than hundred times compared to the traditional BER measurement for the same accuracy. To implement the proposed BER estimation methodology, we have developed a novel time-to-digital converter (TDC). This design effectively measures the delay between two signals and converts it into the digital format. Performance of the TDC has been evaluated and presented using ModelSim and SPICE simulation.