TURBO CODING IMPLEMENTED IN A FINE GRAINED PROGRAMABLE GATE ARRAY ARCHITECTURE

Abstract

One recent method to approach the capacity of a channel is Turbo Coding. However, a major concern with the implementation of a Turbo Code is the overall complexity and real-time throughput of the digital hardware system. The salient design problem of Turbo Coding is the iterative decoder, which must perform calculations over all possible states of the trellis. Complex computations such as exponentiations, logarithms and division are explored as part of this research to compare the complexity of the traditionally avoided maximum a-posteriori probability (MAP) decoder to that of the more widely accepted and simplified Logarithm based MAP decoder (LOG-MAP). This research considers the fine grained implementation and processing of MAP, LOG-MAP and a hybrid LOG-MAP-Log Likelihood Ratio (LLR) based Turbo Codes on a Xilinx Virtex 4 PGA. Verification of the Turbo Coding system performance is demonstrated on a Xilinx Virtex 4 ML402SX evaluation board with the EDA of the Xilinx System Generator utilizing hardware co-simulation. System throughput and bit error rate (BER) are the performance metrics that are evaluated as part of this research. An efficient system throughput is predicated by the parallel design of the decoder and BER is determined by data frame size, data word length and the number of decoding iterations. Furthermore, traditional and innovative stopping rules are evaluated as part of this research to facilitate the number of iterations required during decoding.