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Performance of the Xilinx Zynq System-on-Chip Interconnect with Asymmetric Multiprocessing
Powell, Andrew Andre
Powell, Andrew Andre
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Thesis/Dissertation
Date
2014
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Electrical and Computer Engineering
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http://dx.doi.org/10.34944/dspace/3401
Abstract
For many applications, embedded designers need to construct systems that facilitate real-time constraints and thus require complete information on a processor's performance under specified parameters. An important and limiting factor in any processor's performance is how quickly components are able to intercommunicate over the system's bus. However, another important constraint, specific to real-time systems, is knowing precisely how long the data communication will require. A highly integrated system composed of multiple processing cores, referred to as a System-on-Chip (SoC) device, contains a bus known as an on-chip interconnect. Specifically, this thesis research presents how rapidly the AMBA AXI on-chip interconnect of Xilinx Zynq-7000 Extensible Processing Platform (EPP) SoC device functions by measuring the time required to communicate between memory and the two major device components of the SoC device. The memory is either internal or external. The two major device components include the processing system (PS) and programmable logic (PL). The PS contains a dual-core ARM Cortex-A9 processor that executes FreeRTOS in Asymmetric Multiprocessing. Communication between the PL and memory is through the PS-PL interfaces; the Accelerator Coherency Port AXI interface, High Performance AXI interface, and the General Purpose AXI interface. The benchmarking is performed under several, changing parameters; such as the payload size and the number of devices executing in the PL. The embedded design is implemented with Xilinx Vivado Design Suite, which includes the Vivado IDE and the SDK, and is executed on the Avnet ZedBoard and Xilinx ZC702 Evaluation Kit.
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